Semiconductor device

ABSTRACT

A semiconductor device includes a plurality of active patterns protruding from a substrate, a gate structure intersecting the plurality of active patterns, a plurality of source/drain regions respectively on the plurality of active patterns at opposite sides of the gate structure, and source/drain contacts intersecting the plurality of active patterns, each of the source/drain contacts connected in common to the source/drain regions thereunder, each of the plurality of source/drain regions including a first portion in contact with a top surface of the active pattern thereunder, the first portion having a width substantially increasing as a distance from the substrate increases, and a second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the substrate increases, bottom surfaces of the source/drain contacts being lower than an interface between the first and second portions.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2015-0043085, filed on Mar. 27, 2015,in the Korean Intellectual Property Office, and entitled: “SemiconductorDevice,” is incorporated by reference herein in its entirety.

BACKGROUND

1. Field

Embodiments relate to a semiconductor device and, more particularly, toa semiconductor device including a fin field effect transistor.

2. Description of the Related Art

A semiconductor device may include an integrated circuit includingmetal-oxide-semiconductor field effect transistors (MOSFETs). As sizesand design rules of semiconductor devices have been reduced, sizes ofMOSFETs have also been scaled down. Operating characteristics ofsemiconductor devices may be deteriorated by the scale down of theMOSFETs. Thus, various researches are being conducted for semiconductordevices capable of overcoming limitations caused by a high integrationdensity and of improving performance.

SUMMARY

Embodiments provide a semiconductor device capable of optimizingelectrical characteristics and of improving reliability.

In one aspect, a semiconductor device may include a plurality of activepatterns protruding from a substrate, a gate structure intersecting theplurality of active patterns, a plurality of source/drain regionsrespectively disposed on the plurality of active patterns at both sidesof the gate structure, and source/drain contacts intersecting theplurality of active patterns. Each of the source/drain contacts may beconnected in common to the source/drain regions disposed thereunder.Each of the plurality of source/drain regions may include a firstportion being in contact with a top surface of the active patterndisposed thereunder and having a width substantially increasing as adistance from the substrate increases, and a second portion extendingfrom the first portion and having a width substantially decreasing as adistance from the substrate increases. Bottom surfaces of thesource/drain contacts may be lower than an interface between the firstand second portions.

In an embodiment, the bottom surfaces of the source/drain contacts maybe higher than the top surfaces of the plurality of the active patterns.

In an embodiment, the bottom surfaces of the source/drain contacts maybe flat surfaces substantially parallel to a top surface of thesubstrate.

In an embodiment, the bottom surfaces of the source/drain contacts mayinclude uneven and curved surfaces.

In an embodiment, the plurality of active patterns may be spaced apartfrom each other at substantially equal distances.

In an embodiment, each of the source/drain regions may further include athird portion disposed at a lower level than the top surfaces of theplurality of active patterns. The third portion may be in contact withsidewalls of the active pattern disposed under each of the source/drainregions. A lowermost end of the third portion may be spaced apart fromthe sidewalls of the active pattern.

In an embodiment, the source/drain regions may include a material ofwhich a lattice constant is substantially equal to or smaller than thatof the substrate.

In an embodiment, the source/drain regions may include a material ofwhich a lattice constant is greater than that of the substrate.

In an embodiment, the semiconductor device may further include a deviceisolation pattern disposed on the substrate to partially cover sidewallsof the plurality of active patterns. The device isolation pattern mayinclude a first region under the gate structure, and second regions atboth sides of the gate structure. At least one of the second regions mayinclude a plurality of recess regions having bottom surfaces lower thana top surface of the first region.

In an embodiment, the plurality of recess regions may include firstrecess regions between the plurality of active patterns, and secondrecess regions at both sides of the plurality of active patterns. Bottomsurfaces of the first recess regions may be higher than bottom surfacesof the second recess regions.

In an embodiment, the bottom surfaces of the first recess regions may bedisposed at the substantially same height.

In an embodiment, the first recess regions may include an air gap.

In an embodiment, at least one of the source/drain contacts may includean extension extending into the air gap.

In an embodiment, the semiconductor device may further include a contactetch stop layer covering inner surfaces of the first and second recessregions and extending onto the plurality of source/drain regions andsidewalls of the gate structure. The air gap may be defined by thecontact etch stop layer.

In an embodiment, the gate structure may include a gate electrodeintersecting the plurality of active patterns, and a gate dielectricpattern disposed between the gate electrode and the plurality of activepatterns. The gate dielectric pattern may a first sub-gate dielectricpattern, and a second sub-gate dielectric pattern of which a dielectricconstant is higher than that of the first sub-gate dielectric pattern.

In another aspect, a semiconductor device may include a substrateincluding a first region and a second region different from each other,a plurality of first active patterns protruding from the substrate ofthe first region and spaced apart from each other at equal distances, aplurality of second active patterns protruding from the substrate of thesecond region and spaced apart from each other at different distances, afirst gate structure intersecting the plurality of first activepatterns, a second gate structure intersecting the plurality of secondactive patterns, a plurality of first source/drain regions respectivelydisposed on the plurality of first active patterns disposed at one sideof the first gate structure, a plurality of second source/drain regionsrespectively disposed on the plurality of second active patternsdisposed at one side of the second gate structure, a first source/draincontact intersecting the plurality of first active patterns andconnected in common to the plurality of first source/drain regions, anda second source/drain contact intersecting the plurality of secondactive patterns and connected in common to the plurality of secondsource/drain regions. A top surface of the first source/drain contactmay be lower than a top surface of the second source/drain contact.

In an embodiment, a bottom surface of the first source/drain contact maybe a flat surface substantially parallel to a top surface of thesubstrate.

In an embodiment, a bottom surface of the second source/drain contactmay include a plurality of flat surfaces and a plurality of inclinedsurfaces.

In an embodiment, the bottom surface of the first source/drain contactmay be lower than an uppermost one of the plurality of flat surfaces.

In an embodiment, the first gate structure may include a first gateelectrode intersecting the plurality of first active patterns, and afirst gate dielectric pattern disposed between the first gate electrodeand the plurality of first active patterns. The second gate structuremay include a second gate electrode intersecting the plurality of secondactive patterns, and a second gate dielectric pattern disposed betweenthe second gate electrode and the plurality of second active patterns. Atop surface of the first gate electrode may be lower than a top surfaceof the second gate electrode.

In an embodiment, a width of the first gate electrode may be greaterthan a width of the second gate electrode.

In an embodiment, the first gate dielectric pattern may include a firstsub-gate dielectric pattern, and a second sub-gate dielectric pattern ofwhich a dielectric constant is higher than that of the first sub-gatedielectric pattern.

In an embodiment, the second gate dielectric pattern may include thesame material as the second sub-gate dielectric pattern.

In an embodiment, each of the plurality of first source/drain regionsmay include a first portion being in contact with a top surface of thefirst active pattern disposed thereunder and having a widthsubstantially increasing as a distance from the substrate increases, anda second portion extending from the first portion and having a widthsubstantially decreasing as a distance from the substrate increases. Abottom surface of the first source/drain contact may be lower than aninterface between the first and second portions.

In an embodiment, the bottom surface of the first source/drain contactmay be higher than the top surfaces of the plurality of first activepatterns.

In an embodiment, each of the plurality of first source/drain regionsmay further include a third portion disposed at a lower level than thetop surfaces of the plurality of first active patterns. The thirdportion may be in contact with sidewalls of the first active patterndisposed under each of the first source/drain regions. A lowermost endof the third portion may be spaced apart from the sidewalls of the firstactive pattern.

In an embodiment, the first source/drain regions may include a materialof which a lattice constant is substantially equal to or smaller thanthat of substrate.

In an embodiment, the first source/drain regions may include a materialof which a lattice constant is greater than that of the substrate.

In an embodiment, the plurality of second active patterns may include apair of first sub-active patterns spaced apart from each other by afirst distance, and a second sub-active pattern spaced apart from one ofthe pair of first sub-active patterns by a second distance greater thanthe first distance. The plurality of second source/drain regions mayinclude first, second, and third sub-source/drain regions disposed onthe pair of first sub-active patterns and the second sub-active pattern,respectively. A conductivity type of the first and secondsub-source/drain regions may be different from that of the thirdsub-source/drain region.

In an embodiment, the second source/drain contact may include anextension extending into between the second sub-active pattern and thefirst sub-active pattern adjacent to the second sub-active pattern.

In yet another aspect, a semiconductor device may include a plurality ofactive patterns protruding from a substrate, a gate structureintersecting the plurality of active patterns, a plurality ofsource/drain regions respectively on the plurality of active patterns atopposite sides of the gate structure; and source/drain contactsintersecting the plurality of active patterns, each of the source/draincontacts being connected in common to the source/drain regionsthereunder, wherein each of the plurality of source/drain regionsincludes at least one sidewalls with a triangular profile, thetriangular profile having a sharp edge extending away from a sidewall ofa corresponding source/drain contact, and wherein distances between abottom of the substrate and corresponding lowermost surfaces of thesource/drain contacts are smaller than respective distances of thebottom of the substrate and corresponding sharp edges.

Each of the plurality of source/drain regions may include a firstportion in contact with a top surface of the active pattern thereunder,the first portion having a width substantially increasing as a distancefrom the bottom of the substrate increases, and a second portionextending from the first portion, the second portion having a widthsubstantially decreasing as a distance from the bottom of the substrateincreases, wherein the sharp edges of the triangular profiles are at aninterface between the first an second portions.

The semiconductor device may further include air gaps among theplurality of source/drain regions, each source/drain contact being on atleast one corresponding air gap.

At least one of bottom surfaces of the source/drain contacts may have adifferent profile than other source/drain contacts.

The at least one of the bottom surfaces of the source/drain contactshaving a different profile may have a larger contact area with acorresponding source/drain region thereunder.

BRIEF DESCRIPTION OF THE DRAWINGS

Features will become apparent to those of ordinary skill in the art bydescribing in detail exemplary embodiments with reference to theattached drawings, in which:

FIG. 1 illustrates a plan view of a semiconductor device according toexample embodiments.

FIG. 2A illustrates a cross-sectional view taken along lines I-I′, A-A′,and B-B′ of FIG. 1.

FIG. 2B illustrates a cross-sectional view taken along lines and C-C′ ofFIG. 1.

FIG. 2C illustrates a cross-sectional view taken along lines IV-IV′ andD-D′ of FIG. 1.

FIGS. 3A, 3B, 3C, and 3D illustrate enlarged views corresponding to aportion ‘A’ of FIG. 2C.

FIGS. 4A, 4B, and 4C illustrate enlarged views corresponding to aportion ‘13’ of FIG. 2C.

FIGS. 5A to 10A illustrate cross-sectional views along lines I-I′, A-A′,and B-B′ of FIG. 1 to illustrate stages in a method for manufacturing asemiconductor device according to example embodiments.

FIGS. 5B to 10B illustrate cross-sectional views along lines and C-C′ ofFIG. 1.

FIGS. 5C to 10C illustrate cross-sectional views along lines IV-IV′ andD-D′ of FIG. 1.

FIG. 11 illustrates an equivalent circuit diagram of a complementarymetal-oxide-semiconductor static random access memory cell (CMOS SRAMcell) including a field effect transistor according to exampleembodiments.

FIG. 12 illustrates a schematic block diagram of an electronic systemincluding a semiconductor device according to embodiments.

FIG. 13 illustrates a schematic block diagram of an electronic deviceincluding a semiconductor device according to embodiments.

FIG. 14 illustrates a mobile phone implemented with an electronic systemaccording to embodiments.

FIG. 15 illustrates a tablet or smart tablet implemented with anelectronic system according to embodiments.

FIG. 16 illustrates a notebook computer implemented with an electronicsystem according to embodiments.

DETAILED DESCRIPTION

Example embodiments will now be described more fully hereinafter withreference to the accompanying drawings; however, they may be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey exemplary implementations to those skilled in the art. In thedrawing figures, the dimensions of layers and regions may be exaggeratedfor clarity of illustration.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to limit. As used herein, thesingular terms “a,” “an” and “the” are intended to include the pluralforms as well, unless the context clearly indicates otherwise. As usedherein, the term “and/or” includes any and all combinations of one ormore of the associated listed items.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it may be directlyconnected or coupled to the other element or intervening elements may bepresent. Similarly, it will be understood that when an element such as alayer, region or substrate is referred to as being “on” another element,it can be directly on the other element or intervening elements may bepresent. In contrast, the term “directly” means that there are nointervening elements.

It will be further understood that the terms “comprises”, “comprising,”,“includes” and/or “including”, when used herein, specify the presence ofstated features, integers, steps, operations, elements, and/orcomponents, but do not preclude the presence or addition of one or moreother features, integers, steps, operations, elements, components,and/or groups thereof.

Additionally, the embodiment in the detailed description will bedescribed with sectional views as ideal exemplary views. Accordingly,shapes of the exemplary views may be modified according to manufacturingtechniques and/or allowable errors. Therefore, the embodiments includeother shapes that may be created according to manufacturing processes.Areas exemplified in the drawings have general properties, and are usedto illustrate specific shapes of elements that are not limited only tothose illustrated. For example, an etching region illustrated as arectangle may have rounded or curved features. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to limit.

It will be also understood that although the terms first, second, thirdetc. may be used herein to describe various elements, these elementsshould not be limited by these terms. These terms are only used todistinguish one element from another element. Thus, a first element insome embodiments could be termed a second element in other embodimentswithout departing from the teachings of the present disclosure.Exemplary embodiments explained and illustrated herein include theircomplementary counterparts. The same reference numerals or the samereference designators denote the same elements throughout thespecification.

Further, devices and methods of forming devices according to variousembodiments described herein may be embodied in microelectronic devicessuch as integrated circuits, wherein a plurality of devices according tovarious embodiments described herein are integrated in the samemicroelectronic device. Accordingly, the cross-sectional view(s)illustrated herein may be replicated in two different directions, whichneed not be orthogonal, in the microelectronic device. Thus, a plan viewof the microelectronic device that embodies devices according to variousembodiments described herein may include a plurality of the devices inan array and/or in a two-dimensional pattern that is based on thefunctionality of the microelectronic device.

The devices according to various embodiments described herein may beinterspersed among other devices depending on the functionality of themicroelectronic device. Moreover, microelectronic devices according tovarious embodiments described herein may be replicated in a thirddirection that may be orthogonal to the two different directions, toprovide three-dimensional integrated circuits.

Accordingly, the cross-sectional view(s) illustrated herein providesupport for a plurality of devices according to various embodimentsdescribed herein that extend along two different directions in a planview and/or in three different directions in a perspective view. Forexample, when a single active region is illustrated in a cross-sectionalview of a device/structure, the device/structure may include a pluralityof active regions and transistor structures (or memory cell structures,gate structures, etc., as appropriate to the case) thereon, as would beillustrated by a plan view of the device/structure.

FIG. 1 is a plan view illustrating a semiconductor device according toexample embodiments. FIG. 2A is a cross-sectional view taken along linesI-I′, A-A′, and B-B′ of FIG. 1. FIG. 2B is a cross-sectional view takenalong lines III-III′ and C-C′ of FIG. 1. FIG. 2C is a cross-sectionalview taken along lines IV-IV′ and D-D′ of FIG. 1. FIGS. 3A, 3B, 3C, and3D are enlarged views corresponding to a portion ‘A’ of FIG. 2C. FIGS.4A, 4B, and 4C are enlarged views corresponding to a portion ‘B’ of FIG.2C.

Referring to FIGS. 1, 2A, 2B, 2C, 3A, and 4A, a substrate 100 includinga first region R1 and a second region R2 may be provided. The substrate100 may be a semiconductor substrate. For example, the substrate 100 maybe a silicon substrate, a germanium substrate, or a silicon-on-insulator(SOI) substrate. According to an embodiment, the first region R1 may bea portion of a logic cell region in which logic transistors constitutinga logic circuit are disposed. For example, the first region R1 may be aregion in which logic transistors constituting a process core or aninput/output (I/O) terminal are disposed. However, embodiments are notlimited thereto. The second region R2 may be a portion of a memory cellregion in which a plurality of memory cells for storing data are formed.For example, memory cell transistors constituting a plurality of 6Tstatic random access memory (6T SRAM) cells may be formed in the secondregion R2. Each of the 6T SRAM cells may consist of six transistors.However, embodiments are not limited thereto.

Each of the regions R1 and R2 may include an NMOSFET region NR1 or NR2and a PMOSFET region PR1 or PR2. In the present embodiment, the NMOSFETregion NR1 or NR2 may be defined as an active region on which one N-typetransistor is disposed, and the PMOSFET region PR1 or PR2 may be definedas an active region on which one P-type transistor is disposed. TheNMOSFET region NR1 or NR2 and the PMOSFET region PR1 or PR2 of each ofthe regions R1 and R2 may be arranged in, e.g., a first direction D1.However, embodiments are not limited thereto.

Active patterns may be provided on each of the regions R1 and R2. Indetail, first active patterns AP1 protruding from the substrate 100 maybe disposed on each of the active regions NR1 and PR1 of the firstregion R1. The first active patterns AP1 may be arranged, e.g., spacedapart from each other, in the first direction D1 and may have lineshapes extending in a second direction D2 intersecting the firstdirection D1. The first active patterns AP1 of each of the activeregions NR1 and PR1 may be spaced apart from each other at substantiallyequal distances. For example, the first active patterns AP1 of each ofthe active regions NR1 and PR1 may be spaced apart from each other by afirst distance d1. Each of the first active patterns AP1 may be aportion of the substrate 100 or an epitaxial layer formed on thesubstrate 100. For example, three first active patterns AP1 are disposedon each of the active regions NR1 and PR1 of the first region R1 inFIG. 1. However, embodiments are not limited thereto, e.g., four or morefirst active patterns AP1 arranged at equal distances may be disposed oneach of the active regions NR1 and PR1 of the first region R1.

A second active pattern AP2 may be disposed on each of the activeregions NR2 and PR2 of the second region R2. The second active patternsAP2 may be arranged, e.g., spaced apart from each other, in the firstdirection D1 and may have line shapes extending in the second directionD2. Each of the second active patterns AP2 may be a portion of thesubstrate 100 or an epitaxial layer formed on the substrate 100.According to example embodiments, the second active pattern AP2 may beprovided in plurality on the NMOSFET region NR2 of the second region R2.For example, two second active patterns AP2 may be disposed on theNMOSFET region NR2. However, embodiments are not limited thereto, e.g.,three or more second active patterns AP2 may be provided on the NMOSFETregion NR2. In this case, the three or more second active patterns AP2may be spaced apart from each other at substantially equal distances.For example, one second active pattern AP2 may be disposed on thePMOSFET region PR2 of the second region R2. However, embodiments are notlimited thereto, e.g., a plurality of second active patterns AP2 may bedisposed on the PMOSFET PR2 of the second region R2.

According to example embodiments, the second active patterns AP2 of theNMOSFET region NR2 may be spaced apart from each other by a seconddistance d2, and the second active pattern AP2 of the PMOSFET region PR2may be spaced apart from the second active pattern AP2 of the NMOSFETregion NR2 adjacent to the PMOSFET region PR2 by a third distance d3.The third distance d3 may be greater than the second distance d2. Thethird distance d3 may be a minimum distance necessary to isolate theNMOSFET region NR2 from the PMOSFET region PR2 having a differentconductivity type from the NMOSFET region NR2. Meanwhile, the seconddistance d2 may be greater than the first distance d1. Hereinafter, apair of second active patterns AP2 on the NMOSFET region NR2 and onesecond active pattern AP2 on the PMOSFET region PR2 will be described asan example for the purpose of ease and convenience in explanation.

Device isolation patterns may be disposed on the substrate 100. Thedevice isolation patterns may include first and second device isolationpatterns ST1 and ST2 of the first region R1 and third device isolationpatterns ST3 of the second region R2 (FIG. 2B). The first deviceisolation pattern ST1 may isolate the NMOSFET region NR1 and the PMOSFETregion PR1 of the first region R1 from each other. For example, theNMOSFET region NR1 and the PMOSFET region PR1 may be spaced apart fromeach other in the first direction D1 with the first device isolationpattern ST1 interposed therebetween. The second device isolationpatterns ST2 extending in the second direction D2 may be disposed atboth sides of each of the first active patterns AP1. The first andsecond device isolation patterns ST1 and ST2 may correspond to portionsof an insulating layer formed in one body.

Each of the first and second device isolation patterns ST1 and ST2 mayinclude a first portion P1 disposed under a first gate structure GS1(FIG. 2B) to be described later, and second portions P2 disposed at bothsides of the first gate structure GS1 (FIG. 2C). The first portions P1of the second device isolation patterns ST2 may expose upper portions ofthe first active patterns AP1 disposed under the first gate structureGS1. The upper portions of the first active patterns AP1, which areexposed by the first portions P1, may be defined as first active finsAF1. According to example embodiments, upper portions of the secondportions P2 of the first and second device isolation patterns ST1 andST2 may be recessed. In other words, the second portions P2 may includea plurality of recess regions. For example, as illustrated in FIG. 3A,the plurality of recess regions may include first, second, and thirdrecess regions RS1, RS2, and RS3 disposed at one side of the first gatestructure GS1. The first recess regions RS1 may be disposed between thefirst active patterns AP1 of the NMOSFET region NR1, and the secondrecess regions RS2 may be disposed between the first active patterns AP1of the PMOSFET region PR1. The third recess region RS3 may be formed ata side of the first active pattern AP1, adjacent to the first deviceisolation pattern ST1, of each of the active regions NR1 and PR1.

Recessed depths of the first to third recess regions RS1 to RS3 may bedifferent from each other by a pattern density. In other words, a recessregion between first active patterns AP1 spaced apart from each other bya relatively small distance may be shallower than a recess regionbetween the first active patterns AP1 spaced apart from each other by arelatively great distance. For example, bottom surfaces BS1 of the firstrecess regions RS1 may be higher, e.g., at a larger distance from abottom of the substrate 100, than a bottom surface BS3 of the thirdrecess region RS3. In addition, bottom surfaces BS2 of the second recessregions RS2 may also be higher, e.g., at a larger distance from a bottomof the substrate 100, than the bottom surface BS3 of the third recessregion RS3. Furthermore, the bottom surfaces BS1 of the first recessregions RS1 may be disposed at a substantially same height as eachother. Likewise, the bottom surfaces BS2 of the second recess regionsRS2 may be disposed at a substantially same height as each other. Thisis because the first active patterns AP1 of each of the active regionsNR1 and PR1 are arranged at equal distances. In some embodiments, thesecond portions P2 may expose sidewalls of the first active patterns AP1of the NMOSFET region NR1 disposed at both sides of the first gatestructure GS1 but may not expose sidewalls of the first active patternsAP1 of the PMOSFET region PR1 disposed at both sides of the first gatestructure GS1. However, embodiments are not limited thereto. The firstand second device isolation patterns ST1 and ST2 may include, e.g.,silicon oxide.

Each of the third device isolation patterns ST3 may include a thirdportion P3 (FIG. 2B) disposed under a second gate structure GS2, andfourth portions P4 disposed at both sides of the second gate structureGS2. The third portions P3 of the third device isolation patterns ST3may expose upper portions of the second active patterns AP2 disposedunder the second gate structure GS2. The upper portions of the secondactive patterns AP2, which are exposed by the third portions P3, may bedefined as second active fins AF2. According to example embodiments,upper portions of the fourth portions P4 of the third device isolationpatterns ST3 may be recessed.

In other words, the fourth portions P4 may include a plurality of recessregions. For example, the plurality of recess regions of the fourthportions P4 may include fourth, fifth, and sixth recess regions RS4,RS5, and RS6 disposed at one side of the second gate structure GS2 (FIG.4A). The fourth recess region RS4 may be disposed between the secondactive patterns AP2 of the NMOSFET region NR2, and the fifth recessregion RS5 may be formed between the second active pattern AP2 of thePMOSFET region PR2 and the second active pattern AP2 of the NMOSFETregion NR2 adjacent thereto. The sixth recess regions RS6 may berespectively disposed at both sides of the three second active patternsAP2 of the second region R2. Recessed depths of the fourth to sixthrecess regions RS4 to RS6 may be different from each other by a patterndensity. For example, a bottom surface BS4 of the fourth recess regionRS4 may be higher than bottom surfaces BS5 and BS6 of the fifth andsixth recess regions RS5 and RS6. According to some embodiments, thefourth portions P4 may expose sidewalls of the second active patternsAP2 of the NMOSFET region NR2 disposed at both sides of the second gatestructure GS2 but may not expose sidewalls of the second active patternAP2 of the PMOSFET region PR2 disposed at both sides of the second gatestructure GS2. However, embodiments are not limited thereto. The thirddevice isolation patterns ST3 may include, e.g., silicon oxide.

As illustrated in FIG. 1, the first gate structure GS1 may be disposedon the substrate 100 of the first region R1 to intersect the firstactive patterns AP1, and the second gate structure GS2 may be disposedon the substrate 100 of the second region R2 to intersect the secondactive patterns AP2. The first gate structure GS1 may extend in thefirst direction D1 to intersect the NMOSFET region NR1 and the PMOSFETregion PR1 of the first region R1, and the second gate structure GS2 mayextend in the first direction D1 to intersect the NMOSFET region NR2 andthe PMOSFET region PR2 of the second region R2. Referring to FIG. 2A,first gate spacers 121 a may be disposed on both sidewalls of the firstgate structure GS1 to extend along the first gate structure GS1 in thefirst direction D1, and second gate spacers 121 b may be disposed onboth sidewalls of the second gate structure GS2 to extend along thesecond gate structure GS2 in the first direction D1. The first andsecond gate spacers 121 a and 121 b may include a nitride, e.g., siliconnitride. In the present embodiment, the second gate structure GS2intersects all the second active patterns AP2 of the active regions NR2and PR2. However, embodiments are not limited thereto, e.g., the secondgate structure GS2 may intersect the second active patterns AP2 of theNMOSFET region NR2 but may not be disposed on the second active patternAP2 of the PMOSFET region PR2.

The first gate structure GS1 may include a first gate electrode GE1covering top surfaces and sidewalls of the first active fins AF1 and afirst gate dielectric pattern GD1 disposed between the first gateelectrode GE1 and the first gate spacer 121 a (FIG. 2B). The first gatedielectric pattern GD1 may also be disposed between the first gateelectrode GE1 and the first active fins AF1, and may horizontally extendfrom the first active fins AF1 to cover top surfaces of the firstportions P1 of the first and second device isolation patterns ST1 andST2. In some embodiments, the first gate dielectric pattern GD1 mayinclude a first sub-gate dielectric pattern GD1 a adjacent to the firstgate spacers 121 a and the first active fins AF1, and a second sub-gatedielectric pattern GD2 a adjacent to the first gate electrode GE1. Thefirst and second sub-gate dielectric patterns GD1 a and GD2 a may havedifferent dielectric constants from each other. In other words, thedielectric constant of the second sub-gate dielectric pattern GD2 a maybe higher than that of the first sub-gate dielectric pattern GD1 a. Forexample, the first sub-gate dielectric pattern GD1 a may include asilicon oxide layer or a silicon oxynitride layer, and the secondsub-gate dielectric pattern GD2 a may include at least one of high-kdielectric layers of which dielectric constants are higher than that ofsilicon oxide. For example, the high-k dielectric layers may include,but not limited to, a hafnium oxide layer, a hafnium silicate layer, azirconium oxide layer, and a zirconium silicate layer. The first gateelectrode GE1 may include at least one of a conductive metal nitride,e.g., titanium nitride or tantalum nitride, or a metal, e.g., aluminumor tungsten. Hereinafter, the first active fins AF1 of the NMOSFETregion NR1 under the first gate structure GS1 may be defined as firstchannel regions CH1, and the first active fins AF1 of the PMOSFET regionPR1 under the first gate structure GS1 may be defined as second channelregions CH2 (FIG. 2A).

The second gate structure GS2 may include a second gate electrode GE2covering top surfaces and sidewalls of the second active fins AF2, and asecond gate dielectric pattern GD2 disposed between the second gateelectrode GE2 and the second gate spacer 121 b. The second gatedielectric pattern GD2 may also be disposed between the second gateelectrode GE2 and the second active fins AF2, and may horizontallyextend from the second active fins AF2 to cover top surfaces of thethird portions P3 of the third device isolation patterns ST3. The secondgate electrode GE2 may include the same material as the first gateelectrode GE1. In other words, the second gate electrode GE2 may includeat least one of a conductive metal nitride, e.g., titanium nitride ortantalum nitride, or a metal, e.g., aluminum or tungsten. The secondgate dielectric pattern GD2 may include the substantially same materialas the second sub-gate dielectric pattern GD2 a. In other words, thesecond gate dielectric pattern GD2 may include at least one of high-kdielectric layers of which dielectric constants are higher than that ofsilicon oxide. Hereinafter, the second active fins AF2 of the NMOSFETregion NR2 under the second gate structure GS2 may be defined as thirdchannel regions CH3, and the second active fin AF2 of the PMOSFET regionPR2 under the second gate structure GS2 may be defined as a fourthchannel region CH4.

According to example embodiments, a third width W3 of the first gateelectrode GE1 may be greater than a fourth width W4 of the second gateelectrode GE2. In some embodiments, the third width W3 may be about tenor more times greater than the fourth width W4. For example, the thirdwidth W3 may be about 200 nm, and the fourth width W4 may be 20 nm orless. A top surface GE1S of the first gate electrode GE1 may be lower,e.g., at a smaller distance from the bottom of the substrate 100, than atop surface GE2S of the second gate electrode GE2.

Source/drain regions may be disposed at both sides of each of the firstand second gate structures GS1 and GS2. In detail, the source/drainregions disposed at both sides of the first gate structure GS1 mayinclude first source/drain regions SD1 disposed on the first activepatterns AP1 of the NMOSFET region NR1, and second source/drain regionsSD2 disposed on the first active patterns AP1 of the PMOSFET region PR1.The first source/drain regions SD1 may have N-type conductivity, and thesecond source/drain regions SD2 may have P-type conductivity. In anembodiment, each of the first and second source/drain regions SD1 andSD2 may include an epitaxial pattern formed using the active pattern AP1disposed thereunder as a seed layer. In this case, the firstsource/drain regions SD1 may include a material capable of providing atensile strain to the first channel regions CH1, and the secondsource/drain regions SD2 may include a material capable of providing acompressive strain to the second channel regions CH2. For example, ifthe substrate 100 is a silicon substrate, the first source/drain regionsSD1 may include a silicon carbide (SiC) layer having a smaller latticeconstant than silicon (Si), or a silicon layer having the substantiallysame lattice constant as silicon (Si). The second source/drain regionsSD2 may include a silicon-germanium (SiGe) layer having a greaterlattice constant than silicon (Si). Each of the first channel regionsCH1 may be disposed between the first source/drain regions SD1 adjacentto each other, and each of the second channel regions CH2 may bedisposed between the second source/drain regions SD2 adjacent to eachother.

The source/drain regions disposed at both sides of the second gatestructure GS2 may include third source/drain regions SD3 disposed on thesecond active patterns AP2 of the NMOSFET region NR2, and fourthsource/drain regions SD4 disposed on the second active patterns AP2 ofthe PMOSFET region PR2. The third source/drain regions SD3 may have theN-type conductivity, and the fourth source/drain regions SD4 may havethe P-type conductivity. In an embodiment, each of the third and fourthsource/drain regions SD3 and SD4 may include an epitaxial pattern formedusing the active pattern AP2 disposed thereunder as a seed layer. Inthis case, the third source/drain regions SD3 may include a materialcapable of providing a tensile strain to the third channel regions CH3,and the fourth source/drain regions SD4 may include a material capableof providing a compressive strain to the fourth channel regions CH4. Inother words, the third and fourth source/drain regions SD3 and SD4 mayinclude the same materials as the first and second source/drain regionsSD1 and SD2 described above, respectively. Each of the third channelregions CH3 may be disposed between the third source/drain regions SD3adjacent to each other, and each of the fourth channel regions CH4 maybe disposed between the fourth source/drain regions SD4 adjacent to eachother.

When viewed from a cross-sectional view, the first source/drain regionsSD1 may have a different shape from the second source/drain regions SD2,and the third source/drain regions SD3 may have a different shape fromthe fourth source/drain regions SD4. The shapes of the third and fourthsource/drain regions SD3 and SD4 may correspond to the shapes of thefirst and second source/drain regions SD1 and SD2, respectively. Thesewill be described in detail with reference to FIGS. 3D and 4C. Here,FIGS. 3D and 4C illustrate one cross section of the source/drain regionswhich are not in contact with source/drain contacts CT1 to CT5.

Referring to FIG. 3D, each of the first source/drain regions SD1 mayinclude a first portion LP1 disposed on opposite sidewalls of the firstactive pattern AP1 disposed thereunder, a second portion MP1 having awidth substantially increasing as a distance from the substrate 100increases, and a third portion UP1 having a width substantiallydecreasing as a distance from the substrate 100 increases. The firstportion LP1 may be disposed at a lower level than a top surface of thefirst active pattern AP1 disposed under the first source/drain regionSD1, and may be in contact with the sidewalls of the first activepattern AP1 exposed by the second portions P2 of the second deviceisolation patterns ST2. In addition, a lowermost end LSP1 of the firstportion LP1 may be spaced apart from the above mentioned sidewalls ofthe first active patterns AP1. The second and third portions MP1 and UP1may be disposed at a higher level than the top surface of the firstactive pattern AP1. Here, an interface between the second and thirdportions MP1 and UP1 may be defined as a first interface IS1.

As further illustrated in FIG. 3D, each of the second source/drainregions SD2 may include a first portion LP2 being in contact with thetop surface of the first active pattern AP1 disposed thereunder andhaving a width substantially increasing as a distance from the substrate100 increases, and a second portion UP2 extending from the first portionLP2 and having a width substantially decreasing as a distance from thesubstrate 100 increases. Here, an interface between the first and secondportions LP2 and UP2 of the second source/drain region SD2 may bedefined as a second interface IS2. In some embodiments, uppermost endsUSP1 of the first source/drain regions SD1 may be higher than uppermostends USP2 of the second source/drain regions SD2.

As illustrated in FIG. 4C, the shapes of the third and fourthsource/drain regions SD3 and SD4 may correspond to the shapes of thefirst and second source/drain regions SD1 and SD2, respectively. Indetail, each of the third source/drain regions SD3 may include a firstportion LP3 disposed on opposite sidewalls of the second active patternAP2 disposed thereunder, a second portion MP3 having a widthsubstantially increasing as a distance from the substrate 100 increases,and a third portion UP3 having a width substantially decreasing as adistance from the substrate 100 increases. At this time, the firstportion LP3 may be disposed at a lower level than a top surface of thesecond active pattern AP2 disposed under the third source/drain regionSD3 and may be in contact with the sidewalls of the second activepattern AP2 exposed by the fourth portions P4 of the third deviceisolation patterns ST3. In addition, a lowermost end of the firstportion LP3 may be spaced apart from the above mentioned sidewalls ofthe second active pattern AP2. The second and third portions MP3 and UP3may be disposed at a higher level than the top surface of the secondactive pattern AP2. An interface between the second and third portionsMP3 and UP3 may be defined as a third interface IS3. Further, each ofthe fourth source/drain regions SD4 may include a first portion LP4being in contact with the top surface of the second active pattern AP2disposed thereunder and having a width substantially increasing as adistance from the substrate 100 increases, and a second portion UP4extending from the first portion LP4 and having a width substantiallydecreasing as a distance from the substrate 100 increases. Here, aninterface between the first and second portions LP4 and UP4 of thefourth source/drain region SD4 may be defined as a fourth interface IS4.In some embodiments, uppermost ends USP3 of the third source/drainregions SD3 may be higher than uppermost ends USP4 of the fourthsource/drain regions SD4.

The first gate electrode GE1, the first gate dielectric pattern GD1, andthe first source/drain regions SD1, which are disposed on the NMOSFETregion NR1 of the first region R1, may constitute a first transistor TR1of an N-type. In other words, the first transistor TR1 may be realizedas an N-type multi-fin field effect transistor. Thus, an on-currentcharacteristic of the first transistor TR1 may be improved. The firstgate electrode GE1, the first gate dielectric pattern GD1, and thesecond source/drain regions SD2, which are disposed on the PMOSFETregion PR1 of the first region R1, may constitute a second transistorTR2 of a P-type. In other words, the second transistor TR2 may berealized as a P-type multi-fin field effect transistor. Thus, anon-current characteristic of the second transistor TR2 may be improved.

The second gate electrode GE2, the second gate dielectric pattern GD2,and the third source/drain regions SD3, which are disposed on theNMOSFET region NR2 of the second region R2, may constitute a thirdtransistor TR3 of an N-type. In other words, the third transistor TR3may be realized as an N-type multi-fin field effect transistor. Thus, anon-current characteristic of the third transistor TR3 may be improved.The second gate electrode GE2, the second gate dielectric pattern GD2,and the fourth source/drain regions SD4, which are disposed on thePMOSFET region PR2 of the second region R2, may constitute a fourthtransistor TR4 of a P-type. In other words, the fourth transistor TR4may be realized as a P-type single-fin field effect transistor.

Referring back to FIGS. 1, 2A, 2B, 2C, 3A, and 4A, a contact etch stoplayer 125 may be disposed on the substrate 100. The contact etch stoplayer 125 may cover inner surfaces of the recess regions (e.g., thefirst to sixth recess regions RS1 to RS6) of the first to third deviceisolation patterns ST1, ST2, and ST3 and may extend onto thesource/drain regions SD1 to SD4 and both sidewalls of each of the gatestructures GS1 and GS2. The contact etch stop layer 125 may include amaterial having an etch selectivity with respect to a first interlayerinsulating layer 130 to be described later. For example, the contactetch stop layer 125 may include a silicon nitride layer and/or a siliconoxynitride layer.

The first interlayer insulating layer 130 may be disposed on thesubstrate 100 to cover the source/drain regions SD1 to SD4 and the bothsidewalls of the gate structures GS1 and GS2. A top surface 130S1 of thefirst interlayer insulating layer 130 of the first region R1 may besubstantially coplanar with the top surface GE1S of the first gateelectrode GE1, and a top surface 130S2 of the first interlayerinsulating layer 130 of the second region R2 may be substantiallycoplanar with the top surface GE2S of the second gate electrode GE2. Inother words, the top surface 130S1 of the first interlayer insulatinglayer 130 of the first region R1 may be lower than the top surface 130S2of the first interlayer insulating layer 130 of the second region R2. Insome embodiments, the first interlayer insulating layer 130 of the firstregion R1 may fully fill only a portion of the recess regions (e.g., thefirst to third recess regions RS1 to RS3), in which the contact etchstop layer 125 is formed, of the first region R1.

For example, the first and second recess regions RS1 and RS2 may not befully filled with the first interlayer insulating layer 130. In otherwords, air gaps AG may be formed in the first and second recess regionsRS1 and RS2 (FIGS. 2C and 3A). The air gap AG may be a substantiallyempty space which is not provided with a solid material. Since the spacebetween the first active patterns AP1 is narrow, portions of the contactetch stop layer 125 disposed on the sidewalls of the adjacentsource/drain regions SD1 or SD2 may be connected to each other to formthe air gap AG in each of the first and second recess regions RS1 andRS2. In other words, the air gap AG may be defined by the contact etchstop layer 125 covering the inner surface of each of the first andsecond recess regions RS1 and RS2. Since the air gaps AG are formed inthe first and second recess regions RS1 and RS2, parasitic capacitancesbetween the first active patterns AP1 may be reduced.

According to some embodiments, the first interlayer insulating layer 130of the second region R2 may fully fill the recess regions (e.g., thefourth to sixth recess regions RS4 to RS6) of the second region R2 inwhich the contact etch stop layer 125 is formed. Since the seconddistance d2 between the second active patterns AP2 is smaller than thethird distance d3 but is greater than the first distance d1 between thefirst active patterns AP1, the first interlayer insulating layer 130 mayfully fill the fourth recess region R4 having a narrow width. Accordingto other embodiments, a portion of the recess regions of the secondregion R2 may not be fully filled with the first interlayer insulatinglayer 130. As illustrated in FIG. 4B, the fourth recess region R4 maynot be fully filled with the first interlayer insulating layer 130. Inother words, an air gap AG may be formed in the fourth recess regionRS4. In this case, a parasitic capacitance between the second activepatterns AP2 of the NMOSFET region NR2 may be reduced. For example, thefirst interlayer insulating layer 130 may include at least one of asilicon oxide layer or low-k dielectric layers.

A second interlayer insulating layer 150 may be disposed on thesubstrate 100. The second interlayer insulating layer 150 may cover thefirst interlayer insulating layer 130 and the gate structures GS1 andGS2. According to embodiments, a top surface 150S1 of the secondinterlayer insulating layer 150 of the first region R1 may be lower thana top surface 15052 of the second interlayer insulating layer 150 of thesecond region R2. The second interlayer insulating layer 150 may includeat least one of, e.g., a silicon oxide layer, a silicon nitride layer, asilicon oxynitride layer, or low-k dielectric layers. In someembodiments, a gate capping layer 145 may be disposed between the secondinterlayer insulating layer 150 and the gate structures GS1 and GS2 andbetween the second interlayer insulating layer 150 and the firstinterlayer insulating layer 130. In more detail, the gate capping layer145 of the first region R1 may cover the top surface GE1S of the firstgate electrode GE1 and may extend onto the top surface 130S1 of thefirst interlayer insulating layer 130 of the first region R1. The gatecapping layer 145 of the second region R2 may cover the top surface GE2Sof the second gate electrode GE2 and may extend onto the top surface130S2 of the first interlayer insulating layer 130 of the second regionR2. In other embodiments, unlike the drawings, the gate capping layer145 may be locally disposed on each of the top surfaces GE1S and GE2S ofthe gate electrodes GE1 and GE2 and may not cover the top surfaces 130S1and 130S2 of the first interlayer insulating layer 130. In still otherembodiments, the gate capping layer 145 may be omitted. The gate cappinglayer 145 may include, e.g., a silicon nitride layer.

Source/drain contacts may be disposed at both sides of each of the gatestructures GS1 and GS2. The source/drain contacts may penetrate thesecond interlayer insulating layer 150, the gate capping layer 145, thefirst interlayer insulating layer 130, and the contact etch stop layer125 so as to be connected to the source/drain regions. In more detail,the source/drain contacts of the first region R1 may include firstsource/drain contacts CT1 disposed at both sides of the first gatestructure GS1 of the NMOSFET region NR1, and second source/draincontacts CT2 disposed at both sides of the first gate structure GS1 ofthe PMOSFET region PR1 (FIG. 2A). Each of the first source/draincontacts CT1 may be connected in common to the first source/drainregions SD1 disposed at each side of the first gate structure GS1. Eachof the second source/drain contacts CT2 may be connected in common tothe second source/drain regions SD2 disposed at each side of the firstgate structure GS1. In a plan view, the first source/drain contacts CT1may intersect the first active patterns AP1 of the NMOSFET region NR1and the second source/drain contacts CT2 may intersect the first activepatterns AP1 of the PMOSFET region PR1 (FIG. 1).

Each of the first and second source/drain contacts CT1 and CT2 mayinclude a first conductive pattern 160 a and a second conductive pattern165 a disposed on the first conductive pattern 160 a. The firstconductive pattern 160 a may include a barrier conductive layer. Forexample, the first conductive pattern 160 a may include at least one ofa titanium nitride layer, a tungsten nitride layer, or a tantalumnitride layer. The second conductive pattern 165 a may include a metallayer. For example, the second conductive pattern 165 a may include atleast one of tungsten, titanium, or tantalum. In other embodiments, thefirst and second source/drain contacts CT1 and CT2 may include a dopedsemiconductor material. Even though not shown in the drawings, each ofthe first and second source/drain contacts CT1 and CT2 may furtherinclude a metal silicide layer disposed between the first conductivepattern 160 a and each of the source/drain regions SD1 and SD2. Themetal silicide layer may include at least one of, e.g., titaniumsilicide, tantalum silicide, or tungsten silicide.

The source/drain contacts of the second region R2 may include third andfourth source/drain contacts CT3 and CT4 disposed at one side of thesecond gate structure GS2, and a fifth source/drain contact CT5 disposedat another side of the second gate structure GS2. The third source/draincontact CT3 may be connected in common to the third source/drain regionsSD3 disposed at the one side of the second gate structure GS2, and thefourth source/drain contact CT4 may be connected to the fourthsource/drain region SD4 disposed at the one side of the second gatestructure GS2. The fifth source/drain contact CT5 may be connected incommon to the third and fourth source/drain regions SD3 and SD4 disposedat the another side of the second gate structure GS2. In a plan view,the third source/drain contact CT3 may intersect the second activepatterns AP2 of the NMOSFET region NR2, and the fourth source/draincontact CT4 may intersect the second active pattern AP2 of the PMOSFETregion PR2. The fifth source/drain contact CT5 may intersect the secondactive patterns AP2 of the NMOSFET and PMOSFET regions NR2 and PR2 whenviewed from a plan view.

Each of the third to fifth source/drain contacts CT3, CT4, and CT5 mayinclude a first conductive pattern 160 b and a second conductive pattern165 b disposed on the first conductive pattern 160 b. The firstconductive pattern 160 b may include a barrier conductive layer. Forexample, the first conductive pattern 160 b may include at least one ofa titanium nitride layer, a tungsten nitride layer, or a tantalumnitride layer. The second conductive pattern 165 b may include a metallayer. For example, the second conductive pattern 165 b may include atleast one of tungsten, titanium, or tantalum. In other embodiments, thethird to fifth source/drain contacts CT3 to CT5 may include a dopedsemiconductor material. Even though not shown in the drawings, each ofthe third to fifth source/drain contacts CT3 to CT5 may further includea metal silicide layer disposed between the first conductive pattern 160b and each of the source/drain regions SD3 and SD4. For example, themetal silicide layer may include at least one of titanium silicide,tantalum silicide, or tungsten silicide.

The first and second source/drain contacts CT1 and CT2 may be formed atthe same time to have top surfaces US1 and US2 disposed at thesubstantially same height. Likewise, the third to fifth source/draincontacts CT3 to CT5 may be formed at the same time to have top surfacesUS3 to US5 disposed at the substantially same height. At this time, thetop surfaces US3 to US5 of the third to fifth source/drain contacts CT3to CT5 may be higher than the top surfaces US1 to US2 of the first andsecond source/drain contacts CT1 and CT2. A profile of bottom surfacesof the first to fifth source/drain contacts CT1 to CT5 may be variouslyrealized. Hereinafter, the shapes of the first, second, and fifthsource/drain contacts CT1, CT2, and CT5 will be described in more detailwith reference to some drawings.

First, the shapes of the first and second source/drain contacts CT1 andCT2 will be described with reference to FIGS. 3A, 3B, and 3C. Referringto FIG. 3A, a bottom surface CBS1 of the first source/drain contact CT1may be lower, e.g., relative to the bottom of the substrate 100, thanthe first interfaces IS1 of the first source/drain regions SD1 andhigher, e.g., relative to the bottom of the substrate 100, than the topsurfaces of the first active patterns AP1 which are in contact with thefirst source/drain regions SD1. Likewise, a bottom surface CBS2 of thesecond source/drain contact CT2 may be lower than the second interfacesIS2 of the second source/drain regions SD2 and higher than the topsurfaces of the first active patterns AP1 which are in contact with thesecond source/drain regions SD2. In some embodiments, the bottomsurfaces CBS1 and CBS2 of the first and second source/drain contacts CT1and CT2 may have flat surfaces that are substantially parallel to thetop surface of the substrate 100. In other embodiments, the bottomsurfaces CBS1 and CBS2 of the first and second source/drain contacts CT1and CT2 may have uneven and curved surfaces, as illustrated in FIG. 3B.In this case, an uppermost portion of the bottom surface CBS1 of thefirst source/drain contact CT1 may be lower than the first interfacesIS1 of the first source/drain regions SD1, and a lowermost portion ofthe bottom surface CBS1 of the first source/drain contact CT1 may behigher than the top surfaces of the first active patterns AP1 which arein contact with the first source/drain regions SD1. Likewise, anuppermost portion of the bottom surface CBS2 of the second source/draincontact CT2 may be lower than the second interfaces IS2 of the secondsource/drain regions SD2, and a lowermost portion of the bottom surfaceCBS2 of the second source/drain contact CT2 may be higher than the topsurfaces of the first active patterns AP1 which are in contact with thesecond source/drain regions SD2.

In still other embodiments, as illustrated in FIG. 3C, the first andsecond source/drain contacts CT1 and CT2 may include extensions EP2 thatextend into the recess regions (e.g., the first and second recessregions RS1 and RS2) between the first active patterns AP1. In thiscase, an uppermost portion of the bottom surface CBS1 of the firstsource/drain contact CT1 may be lower than the first interfaces IS1 ofthe first source/drain regions SD1. However, a lowermost portion of thebottom surface CBS1 of the first source/drain contact CT1 may be lowerthan the top surfaces of the first active patterns AP1 which are incontact with the first source/drain regions SD1. In an embodiment, thelowermost portion of the bottom surface CBS1 of the first source/draincontact CT1 may be in contact with the contact etch stop layer 125disposed on the bottom surface BS1 of the first recess region RS1.Likewise, an uppermost portion of the bottom surface CBS2 of the secondsource/drain contact CT2 may be lower than the second interfaces IS2 ofthe second source/drain regions SD2. However, a lowermost portion of thebottom surface CBS2 of the second source/drain contact CT2 may be lowerthan the top surfaces of the first active patterns AP1 which are incontact with the second source/drain regions SD2. In an embodiment, thelowermost portion of the bottom surface CBS2 of the second source/draincontact CT2 may be in contact with the contact etch stop layer 125disposed on the bottom surface BS2 of the second recess region RS2.

Next, referring to FIG. 4A, a bottom surface CBS3 of the fifthsource/drain contact CT5 may include a plurality of flat surfaces (e.g.,first flat surfaces CBS3 a parallel to the bottom of the substrate 100),and a plurality of inclined surfaces (e.g., first inclined surfaces CBS3b at an oblique angle with respect to the bottom of the substrate 100)that extend from the flat surfaces so as to be inclined downward. Inthis case, an uppermost one of the flat surfaces of the bottom surfaceCBS3 of the fifth source/drain contact CT5 may be higher than the thirdinterfaces IS3 of the third source/drain regions SD3 and the fourthinterfaces IS4 of the fourth source/drain regions SD4. On the otherhand, one or some of the inclined surfaces of the bottom surface CBS3 ofthe fifth source/drain contact CT5 may extend to a lower level than thetop surfaces of the second active patterns AP2 which are in contact withthe third and fourth source/drain regions SD3 and SD4. In other words,the fifth source/drain contact CT5 may include an extension EP1extending into the fifth recess region RS5. The extension EP1 of thefifth source/drain contact CT5 may be spaced apart from the secondactive patterns AP2 adjacent thereto. Alternatively, even though notshown in the drawings, the bottom surface CBS3 of the fifth source/draincontact CT5 may be uneven and curved. In this case, an uppermost portionof the bottom surface CBS3 of the fifth source/drain contact CT5 may behigher than the third and fourth interfaces IS3 and IS4. According toembodiments, the bottom surfaces CBS1 and CBS2 of the first and secondsource/drain contacts CT1 and CT2 may be lower than the uppermostportion (or the uppermost surface) of the bottom surface CBS3 of thefifth source/drain contact CT5. Since the fifth source/drain contact CT5has the bottom surface CBS3 described above, a contact area between thefifth source/drain contact CT5 and the source/drain regions mayincrease. As a result, a contact resistance between the fifthsource/drain contact CT5 and the source/drain regions may be reduced toimprove electrical characteristics of the semiconductor device.

Interconnections may be disposed on the second interlayer insulatinglayer 150 so as to be connected to the first to fifth source/draincontacts CT1 to CT5, respectively. The interconnections may beelectrically connected to the first to fourth source/drain regions SD1to SD4 through the first to fifth source/drain contacts CT1 to CT5. Theinterconnections may include a conductive material.

Next, a method for manufacturing a semiconductor device according toexample embodiments will be described with reference to FIGS. 5A to 10A,5B to 10B, and 5C to 10C.

FIGS. 5A to 10A are cross-sectional views taken along lines I-I′,II-II′, A-A′, and B-B′ of FIG. 1 to illustrate a method formanufacturing a semiconductor device according to example embodiments.FIGS. 5B to 10B are cross-sectional views taken along lines III-III′ andC-C′ of FIG. 1. FIGS. 5C to 10C are cross-sectional views taken alonglines IV-IV′ and D-D′ of FIG. 1.

Referring to FIGS. 5A, 5B, and 5C, the substrate 100 including the firstregion R1 and the second region R2 may be provided. The substrate 100may be a semiconductor substrate. For example, the substrate 100 may bea silicon substrate, a germanium substrate, or a SOI substrate.According to an embodiment, the first region R1 may be a portion of alogic cell region in which logic transistors constituting a logiccircuit are disposed. For example, the first region R1 may be a regionin which logic transistors constituting a process core or an I/Oterminal are disposed. However, embodiments are not limited thereto. Thesecond region R2 may be a portion of a memory cell region in which aplurality of memory cells for storing data are formed. For example,memory cell transistors constituting a plurality of 6T static randomaccess memory (6T SRAM) cells may be formed in the second region R2.Each of the 6T SRAM cells may consist of six transistors. However,embodiments are not limited thereto.

Each of the regions R1 and R2 may include the NMOSFET region NR1 or NR2and the PMOSFET region PR1 or PR2. In the present embodiment, theNMOSFET region NR1 or NR2 may be defined as an active region on whichone N-type transistor is disposed, and the PMOSFET region PR1 or PR2 maybe defined as an active region on which one P-type transistor isdisposed. The NMOSFET region NR1 or NR2 and the PMOSFET region PR1 orPR2 of each of the regions R1 and R2 may be arranged in, for example, afirst direction D1. However, embodiments are not limited thereto.

The substrate 100 may be patterned to form shallow trenches 101 definingfirst active patterns AP1 of the first region R1 and second activepatterns AP2 of the second region R2. The first active patterns AP1 maybe arranged in the first direction D1 and may have line shapes extendingin a second direction D2 intersecting the first direction D1. Likewise,the second active patterns AP2 may be arranged in the first direction D1and may have line shapes extending in the second direction D2. The firstactive patterns AP1 may be spaced apart from each other at substantiallyequal distances. For example, the first active patterns AP1 may bespaced apart from each other by the first distance d1. In anotherexample, the second active patterns AP2 of the NMOSFET region NR2 may bespaced apart from each other by a second distance d2, and the secondactive pattern AP2 of the PMOSFET region PR2 may be spaced apart fromthe second active pattern AP2, adjacent to the PMOSFET region PR2, ofthe NMOSFET region NR2 by a third distance d3. The third distance d3 maybe greater than the second distance d2. The third distance d3 may be aminimum distance necessary to isolate the NMOSFET region NR2 from thePMOSFET region PR2 having a different conductivity type from the NMOSFETregion NR2. The second distance d2 may be greater than the firstdistance d1. A necessary first active pattern AP1 a disposed between theNMOSFET and PMOSFET regions NR1 and PR1 may be removed.

A deep trench 103 may be formed between the NMOSFET and PMOSFET regionsNR1 and PR1 during the removal of the necessary first active pattern AP1a. A bottom surface of the deep trench 103 may be lower or deeper than abottom surface of the shallow trench 101.

A first device isolation pattern ST1 may be formed in the deep trench103. In addition, second device isolation patterns ST2 may be formed inthe shallow trenches 101 of the first region R1, and third deviceisolation patterns ST3 may be formed in the shallow trenches 101 of thesecond region R2. The second and third device isolation patterns ST2 andST3 may be formed to expose upper portions of the first active patternsAP1 and upper portions of the second active patterns AP2, respectively.The upper portions of the first and second active patterns AP1 and AP2,which are exposed by the second and third device isolation patterns ST2and ST3, may be defined as first and second active fins AF1 and AF2,respectively. A top surface of the first device isolation pattern ST1may be substantially coplanar with a top surface of the second deviceisolation pattern ST2.

Referring to FIGS. 6A, 6B, and 6C, a first sacrificial gate structuremay be formed on the substrate 100 of the first region R1. The firstsacrificial gate structure may include a first etch stop pattern 105 a,a first sacrificial gate pattern 110 a, and a first gate mask pattern115 a which are sequentially stacked. In addition, a second sacrificialgate structure may be formed on the substrate 100 of the second regionR2. The second sacrificial gate structure may include a second etch stoppattern 105 b, a second sacrificial gate pattern 110 b, and a secondgate mask pattern 115 b which are sequentially stacked. The firstsacrificial gate structure may intersect the first active fins AF1, andthe second sacrificial gate structure may intersect the second activefins AF2. In other words, the first etch stop pattern 105 a and thefirst sacrificial gate pattern 110 a may cover top surfaces andsidewalls of the first active fins AF1 and may extend onto top surfacesof the first and second device isolation patterns ST1 and ST2. The firstgate mask pattern 115 a may be disposed on a top surface of the firstsacrificial gate pattern 110 a to extend along the top surface of thefirst sacrificial gate pattern 110 a. The second etch stop pattern 105 band the second sacrificial gate pattern 110 b may cover top surfaces andsidewalls of the second active fins AF2 and may extend onto top surfacesof the third device isolation patterns ST3. The second gate mask pattern115 b may be disposed on a top surface of the second sacrificial gatepattern 110 b to extend along the top surface of the second sacrificialgate pattern 110 b.

According to embodiments, the first sacrificial gate pattern 110 a mayhave a first width W1, and the second sacrificial gate pattern 110 b mayhave a second width W2 smaller than the first width W1. In someembodiments, an etch stop layer, a sacrificial gate layer, and a gatemask layer may be sequentially formed on the substrate 100 to cover thefirst and second active fins AF1 and AF2, and the gate mask layer, thesacrificial gate layer, and the etch stop layer may be patterned to formthe first and second sacrificial gate structures. The etch sop layer mayinclude. e.g., silicon oxide. The sacrificial gate layer may include amaterial having an etch selectivity with respect to the etch stop layer.For example, the sacrificial gate layer may include poly-silicon. Thesacrificial layer may be formed by a chemical vapor deposition (CVD)process, a physical vapor deposition (PVD), or an atomic layerdeposition (ALD) process. The gate mask layer may include a siliconnitride layer and/or a silicon oxynitride layer.

The first sacrificial gate pattern 110 a may intersect the first activefins AF1 to define a first portion P1 and second portions P2 of each ofthe first and second device isolation patterns ST1 and ST2. The firstportion P1 may correspond to a portion of each of the first and seconddevice isolation patterns ST1 and ST2, which is disposed under the firstsacrificial gate pattern 110 a and overlaps with the first sacrificialgate pattern 110 a. The second portions P2 may correspond to otherportions of each of the first and second device isolation patterns ST1and ST2, which are disposed at both sides of the first sacrificial gatepattern 110 a and are laterally separated from each other by the firstportion P1. Likewise, the second sacrificial gate pattern 110 b mayintersect the second active fins AF2 to define a third portion P3 andfourth portions P4 of each of the third device isolation patterns ST3.The third portion P3 may correspond to a portion of each of the thirddevice isolation patterns ST3, which is disposed under the secondsacrificial gate pattern 110 b and overlaps with the second sacrificialgate pattern 110 b. The fourth portions P4 may correspond to otherportions of each of the third device isolation patterns ST3, which aredisposed at both sides of the second sacrificial gate pattern 110 b andare laterally separated from each other by the third portion P3.

Next, a gate spacer layer 120 may be formed on the substrate 100. Thegate spacer layer 120 may conformally cover the first and secondsacrificial gate patterns 110 a and 110 b. For example, the gate spacerlayer 120 may include silicon nitride. Alternatively, the gate spacerlayer 120 may include a low-k nitride such as silicon carbonitride(SiCN) or silicon oxy-carbonitride (SiOCN). The gate spacer layer 120may be formed by a deposition process such as a CVD process or an ALDprocess.

Referring to FIGS. 7A, 7B, and 7C, upper portions of the first activepatterns AP1 at both sides of the first sacrificial gate pattern 110 aand upper portions of the second active patterns AP2 at both sides ofthe second sacrificial gate pattern 110 b may be removed. Removing theupper portions of the first and second active patterns AP1 and AP2 mayinclude forming a mask pattern on the substrate 100, and performing anetching process using the mask pattern as an etch mask. The etchingprocess may include a drying etching process and/or a wet etchingprocess. The gate spacer layer 120 may also be etched during the removalof the upper portions of the first and second active patterns AP1 andAP2, so first gate spacers 121 a may be formed on both sidewalls of thefirst sacrificial gate pattern 110 a and second gate spacers 121 b maybe formed on both sidewalls of the second sacrificial gate pattern 110b.

According to some embodiments, upper portions of the second portions P2of the first and second device isolation patterns ST1 and ST2 of theNMOSFET region NR1 may be recessed during the removal of the upperportions of the first active patterns AP1, thereby exposing sidewalls ofthe first active patterns AP1 disposed at both sides of the firstsacrificial gate pattern 110 a of the NMOSFET region NR1. On the otherhand, when the upper portions of the second device isolation patternsST2 are recessed, portions of the second device isolation patterns ST2may not be etched but may remain on the sidewalls of the first activepatterns AP1 of the NMOSFET region NR1. The remaining portions of thesecond device isolation patterns ST2 may be defined as first edgeportions ED1. Upper portions of the fourth portions P4 of the thirddevice isolation patterns ST3 of the NMOSFET region NR2 may be recessedduring the removal of the upper portions of the second active patternsAP2, thereby exposing sidewalls of the second active patterns AP2disposed at both sides of the second sacrificial gate pattern 110 b ofthe NMOSFET region NR2. On the other hand, when the upper portions ofthe third device isolation patterns ST3 are recessed, portions of thethird device isolation patterns ST3 may not be etched but may remain onthe sidewalls of the second active patterns AP2 of the NMOSFET regionNR2. The remaining portions of the third device isolation patterns ST3may be defined as second edge portions ED2.

Next, first and second source/drain regions SD1 and SD2 may be formed atboth sides of the first sacrificial gate pattern 110 a, and third andfourth source/drain regions SD3 and SD4 may be formed at both sides ofthe second sacrificial gate pattern 110 b. The first source/drainregions SD1 may be formed on the first active patterns AP1 of theNMOSFET region NR1, and the second source/drain regions SD2 may beformed on the first active patterns AP1 of the PMOSFET region PR1. Thethird source/drain regions SD3 may be formed on the second activepatterns AP2 of the NMOSFET region NR2, and the fourth source/drainregions SD4 may be formed on the second active patterns AP2 of thePMOSFET region PR2. The first to fourth source/drain regions SD1 to SD4may be formed by performing a selective epitaxial growth (SEG) process.In more detail, the first and third source/drain regions SD1 and SD3 mayinclude epitaxial patterns grown using top surfaces and sidewalls of theactive patterns AP1 and AP2 disposed thereunder as seeds. In this case,the first and second source/drain regions SD1 and SD3 may be formed of amaterial capable of providing a tensile strain to the first and secondactive fins AF1 and AF2 disposed therebetween. For example, if thesubstrate 100 is a silicon substrate, the first and second source/drainregions SD1 and SD3 may be formed of silicon (Si) or silicon carbide(SiC). However, embodiments are not limited thereto. The first and thirdsource/drain regions SD1 and SD3 may be doped with dopants during orafter the SEG process. The first and third source/drain regions SD1 andSD3 may be doped with N-type dopants.

On the other hand, the second and fourth source/drain regions SD2 andSD4 may include epitaxial patterns grown using top surfaces of theactive patterns AP1 and AP2 disposed thereunder as seeds. In this case,the second and fourth source/drain regions SD2 and SD4 may be formed ofa material capable of providing a compressive strain to the first andsecond active fins AF1 and AF2 disposed therebetween. For example, ifthe substrate 100 is a silicon substrate, the second and fourthsource/drain regions SD2 and SD4 may be formed of silicon-germanium(SiGe). However, embodiments are not limited thereto. The second andfourth source/drain regions SD2 and SD4 may be doped with dopants duringor after the SEG process. The second and fourth source/drain regions SD2and SD4 may be doped with P-type dopants.

In some embodiments, uppermost ends USP1 of the first source/drainregions SD1 may be higher than uppermost ends USP2 of the secondsource/drain regions SD2. In addition, uppermost ends USP3 of the thirdsource/drain regions SD3 may be higher than uppermost ends USP4 of thefourth source/drain regions SD4. These may be realized by adjustinggrowth rates of the first to fourth source/drain regions SD1 to SD4during the SEG process. Meanwhile, since the edge portions ED1 and ED2are formed, lowermost ends LSP1 and LSP2 of the first and thirdsource/drain regions SD1 and SD3 may be spaced apart from the sidewallsof the first and second active patterns AP1 and AP2.

Referring to FIGS. 8A, 8B, and 8C, upper portions of second and fourthportions P2 and P4 of the first to third device isolation patterns ST1to ST3 may be recessed. As a result, a plurality of recess regions maybe formed in the second and fourth portions P2 and P4 of the first tothird device isolation patterns ST1 to ST3. The plurality of recessregions may be defined by the recessed upper portions of the second andfourth portions P2 and P4. For example, the plurality of recess regionsmay include first, second, and third recess regions RS1, RS2, and RS3disposed at one side of the first sacrificial gate pattern 110 a. Thefirst recess regions RS1 may be disposed between the first activepatterns AP1 of the NMOSFET region NR1, and the second recess regionsRS2 may be disposed between the first active patterns AP1 of the PMOSFETregion PR1. The third recess region RS3 may be formed at a side of thefirst active pattern AP1, adjacent to the first device isolation patternST1, of each of the active regions NR1 and PR1.

Recessed depths of the first to third recess regions RS1 to RS3 may bedifferent from each other according to a pattern density. In otherwords, a recess region between first active patterns AP1 spaced apartfrom each other by a relatively small distance may be shallower than arecess region between the first active patterns AP1 spaced apart fromeach other by a relatively great distance. For example, bottom surfacesBS1 of the first recess regions RS1 may be higher than a bottom surfaceBS3 of the third recess region RS3. In addition, bottom surfaces BS2 ofthe second recess regions RS2 may also be higher than the bottom surfaceBS3 of the third recess region RS3. Furthermore, the bottom surfaces BS1of the first recess regions RS1 may be disposed at the substantiallysame height as each other. Likewise, the bottom surfaces BS2 of thesecond recess regions RS2 may be disposed at the substantially sameheight as each other.

In addition, the plurality of recess regions may further include fourth,fifth, and sixth recess regions RS4, RS5, and RS6 disposed at one sideof the second sacrificial gate pattern 110 b. The fourth recess regionRS4 may be disposed between the second active patterns AP2 of theNMOSFET region NR2, and the fifth recess region RS5 may be formedbetween the second active pattern AP2 of the PMOSFET region PR2 and thesecond active pattern AP2 of the NMOSFET region NR2 adjacent thereto.The sixth recess regions RS6 may be respectively disposed at both sidesof the three second active patterns AP2. As described above, recesseddepths of the fourth to sixth recess regions RS4 to RS6 may be differentfrom each other according to a pattern density. For example, a bottomsurface BS4 of the fourth recess region R4 may be higher than bottomsurfaces BS5 and BS6 of the fifth and sixth recess regions RS5 and RS6.

Thereafter, a contact etch stop layer 125 may be conformally formed onthe substrate 100. The contact etch stop layer 125 may cover innersurfaces of the recess regions of the device isolation patterns ST1 toST3 and may extend onto the first to fourth source/drain regions SD1 toSD4 and the first and second gate mask patterns 115 a and 115 b. Thecontact etch stop layer 125 may be formed of a material having an etchselectivity with respect to a first interlayer insulating layer 130 tobe described later. For example, the contact etch stop layer 125 mayinclude a silicon nitride layer and/or a silicon oxynitride layer. Thecontact etch stop layer 125 may be formed by a CVD process or an ALDprocess.

The first interlayer insulating layer 130 may be formed on the substrate100 having the contact etch stop layer 125. The first interlayerinsulating layer 130 may be formed to cover the source/drain regions SD1to SD4 and the sacrificial gate patterns 110 a and 110 b. The firstinterlayer insulating layer 130 may include at least one of a siliconoxide layer or low-k dielectric layers. Next, a planarization processmay be performed on the first interlayer insulating layer 130 until thetop surfaces of the sacrificial gate patterns 110 a and 110 b areexposed. The planarization process may include an etch-back processand/or a chemical mechanical polishing (CMP) process. The exposedsacrificial gate patterns 110 a and 110 b may be removed to form firstand second gap regions 140 a and 140 b. The first gap region 140 a mayexpose the first active fins AF1 between the first gate spacers 121 a,and the second gap region 140 b may expose the second active fins AF2between the second gate spacers 121 b. The first and second gap regions140 a and 140 b may be formed by selectively etching the sacrificialgate patterns 110 a and 110 b and the etch stop patterns 105 a and 105b.

Referring to FIGS. 9A, 9B, and 9C, a first gate dielectric pattern GD1and a first gate electrode GE1 may be formed to fill the first gapregion 140 a, and a second gate dielectric pattern GD2 and a second gateelectrode GE2 may be formed to fill the second gap region 140 b. In moredetail, a first gate dielectric layer may be formed on the substrate 100to partially fill the first and second gap regions 140 a and 140 b. Thefirst gate dielectric layer may be formed to cover the first and secondactive fins AF1 and AF2. For example, the first gate dielectric layermay include a silicon oxide layer and/or a silicon oxynitride layer.Thereafter, the first gate dielectric layer disposed in the second gapregion 140 b may be selectively removed. Next, a second gate dielectriclayer may be formed on the substrate 100 to partially fill the first andsecond gap regions 140 a and 140 b. The second gate dielectric layer mayinclude at least one of high-k dielectric layers. In some embodiments,the second gate dielectric layer may include at least one of, but notlimited to, a hafnium oxide layer, a hafnium silicate layer, a zirconiumoxide layer, or a zirconium silicate layer. Each of the first and secondgate dielectric layers may be formed by a CVD process or an ALD process.

A gate layer may be formed on the second gate dielectric layer to fillthe rest regions of the first and second gap regions 140 a and 140 b.The gate layer may include at least one of a conductive metal nitride(e.g., titanium nitride or tantalum nitride) or a metal (e.g., aluminumor tungsten). The gate layer, the second gate dielectric layer, and thefirst gate dielectric layer may be planarized to form the first gatedielectric pattern GD1 and the first gate electrode GE1 in the first gapregion 140 a and to form the second gate dielectric pattern GD2 and thesecond gate electrode GE2 in the second gap region 140 b. The first gatedielectric pattern GD1 may include a first sub-gate dielectric patternGD1 a and a second sub-gate dielectric pattern GD2 a which are formedfrom the first gate dielectric layer and the second gate dielectriclayer, respectively. According to embodiments, a height difference mayoccur between a top surface GE1S of the first gate electrode GE1 and atop surface GE2S of the second gate electrode GE2 due to the abovementioned planarization process. In other word, the top surface GE1S ofthe first gate electrode GE1 may be lower than the top surface GE2S ofthe second gate electrode GE2. This may be because an etch rate of thegate layer in the first gap region 140 a may be different from that ofthe gate layer in the second gap region 140 b due to widths of the gapregions 140 a and 140 b during the planarization process of the gatelayer. In other word, since the width W1 of the first gap region 140 ais greater than the width W2 of the second gap region 140 b, the etchrate of the gate layer in the first gap region 140 a may be higher thanthat of the gate layer in the second gap region 140 b.

Top surfaces of the first interlayer insulating layer 130 and the gatespacers 121 a and 121 b may be exposed by the planarization process. Atop surface 130S1 of the planarized first interlayer insulating layer130 of the first region R1 may be substantially coplanar with the topsurface GE1S of the first gate electrode GE1. A top surface 130S2 of theplanarized first interlayer insulating layer 130 of the second region R2may be substantially coplanar with the top surface GE2S of the secondgate electrode GE2. The first gate dielectric pattern GD1 may extendalong a bottom surface of the first gate electrode GE1 and may bedisposed on both sidewalls of the first gate electrode GE1 so as to bedisposed between the first gate electrode GE1 and the first gate spacers121 a. The second gate dielectric pattern GD2 may extend along a bottomsurface of the second gate electrode GE2 and may be disposed on bothsidewalls of the second gate electrode GE2 so as to be disposed betweenthe second gate electrode GE2 and the second gate spacers 121 b.

The first active fins AF1 of the NMOSFET region NR1 under the first gateelectrode GE1 may be defined as first channel regions CH1, and the firstactive fins AF1 of the PMOSFET region PR1 under the first gate electrodeGE1 may be defined as second channel regions CH2. Each of the firstchannel regions CH1 may be disposed between the first source/drainregions SD1, and each of the second channel regions CH2 may be disposedbetween the second source/drain regions SD2. The second active fins AF2of the NMOSFET region NR2 under the second gate electrode GE2 may bedefined as third channel regions CH3, and the second active fins AF2 ofthe PMOSFET region PR2 under the second gate electrode GE2 may bedefined as fourth channel regions CH4. Each of the third channel regionsCH3 may be disposed between the third source/drain regions SD3, and eachof the fourth channel regions CH4 may be disposed between the fourthsource/drain regions SD4. The first gate dielectric pattern GD1 and thefirst gate electrode GE1 may be defined as a first gate structure GS1,and the second gate dielectric pattern GD2 and the second gate electrodeGE2 may be defined as a second gate structure GS2.

Referring to FIGS. 10A, 10B, and 10C, a gate capping layer 145 and asecond interlayer insulating layer 150 may be sequentially formed on theresultant structure including the first and second gate electrodes GE1and GE2. The gate capping layer 145 may cover the gate structures GS1and GS2 and the first interlayer insulating layer 130. For example, thegate capping layer 145 may include a silicon nitride layer. The secondinterlayer insulating layer 150 may include at least one of a siliconoxide layer, a silicon nitride layer, a silicon oxynitride, or low-kdielectric layers. Each of the gate capping layer 145 and the secondinterlayer insulating layer 150 may be formed by, for example, a CVDprocess. Due to the height difference between the first and second gateelectrodes GE1 and GE2, a height difference may also occur between thesecond interlayer insulating layer 150 of the first region R1 and thesecond interlayer insulating layer 150 of the second region R2. In otherwords, a top surface 150S1 of the second interlayer insulating layer 150of the first region R1 may be lower than a top surface 150S2 of thesecond interlayer insulating layer 150 of the second region R2.

Next, first to fifth contact holes H1 to 145 may be formed to penetratethe second interlayer insulating layer 150, the gate capping layer 145,the first interlayer insulating layer 130, and the contact etch stoplayer 125. The first to fifth contact holes H1 to H5 may expose thesource/drain regions SD1 to SD4. The first contact holes H1 may exposethe first source/drain regions SD1 at both sides of the first gatestructure GS1, and the second contact holes H2 may expose the secondsource/drain regions SD2 at both sides of the first gate structure GS1.The third contact hole H3 may expose the third source/drain regions SD3disposed at one side of the second gate structure GS2, and the fourthcontact hole H4 may expose the fourth source/drain region SD4 disposedat the one side of the second gate structure GS2. The fifth contact holeH5 may expose the third and fourth source/drain regions SD3 and SD4disposed at another side of the second gate structure GS2. A maskpattern (not shown) may be formed on the second interlayer insulatinglayer 150, and then, an anisotropic etching process may be performedusing the mask pattern as an etch mask to form the first to fifthcontact holes H1 to H5. In some embodiments, upper portions of the firstto fourth source/drain regions SD1 to SD4 exposed through the first tofifth contact holes H1 to H5 may be partially etched by the anisotropicetching process. According to embodiments, since the first and secondgate electrodes GE1 and GE2 have the height difference, the heightdifference may occur between the top surfaces 130S1 and 130S2 of thefirst interlayer insulating layer 130 of the first and second regions R1and R2. In other words, the top surface 130S1 of the first interlayerinsulating layer 130 of the first region R1 may be lower than the topsurface 130S2 of the first interlayer insulating layer 130 of the secondregion R2. That is, a thickness of the first interlayer insulating layer130 of the first region R1 may be smaller than a thickness of the firstinterlayer insulating layer 130 of the second region R2. Thus, duringthe anisotropic etching process, the first and second source/drainregions SD1 and SD2 may be exposed by the first and second contact holesH1 and H2 before the third and fourth source/drain regions SD3 and SD4are exposed by the third to fifth contact holes H3 to H5. As a result,the upper portions of the first and second source/drain regions SD1 andSD2 may be over-etched, so the first and second contact holes H1 and H2may be formed to have bottom surfaces disposed at a lower level than thefirst and second interfaces IS1 and IS2 of the first and secondsource/drain regions SD1 and SD2. Meanwhile, a bottom surface of thefifth contact hole H5 may have a plurality of flat surfaces and aplurality of inclined surfaces due to an etch rate difference accordingto the pattern density. In addition, the fifth contact hole H5 may beformed to expose the contact etch stop layer 125 disposed on the bottomsurface BS5 of the fifth recess region RS5.

Referring again to FIGS. 2A, 2B, and 2C, first to fifth source/draincontacts CT1 to CT5 may be formed in the first to fifth contact holes H1to H5 of FIGS. 10A and 10C, respectively. Each of the first and secondsource/drain contacts CT1 and CT2 may include a first conductive pattern160 a and a second conductive pattern 165 a disposed on the firstconductive pattern 160 a. Each of the third, fourth, and fifthsource/drain contacts CT3, CT4, and CT5 may include a first conductivepattern 160 b and a second conductive pattern 165 b disposed on thefirst conductive pattern 160 b. In more detail, a conductive materiallayer may be formed on the substrate 100 to fill the first to fifthcontact holes H1 to H5, and then, the conductive material layer may beplanarized until the top surface of the second interlayer insulatinglayer 150 is exposed, thereby forming the first to fifth source/draincontacts CT1 to CT5. In some embodiments, forming the conductivematerial layer may include sequentially depositing a first conductivelayer and a second conductive layer. The first conductive layer mayinclude a barrier conductive layer. For example, the first conductivelayer may include at least one of a titanium nitride layer, a tungstennitride layer, or a tantalum nitride layer. The second conductive layermay include a metal layer. For example, the second conductive layer mayinclude at least one of tungsten, titanium, or tantalum. Even though notshown in the drawings, a thermal treatment process may be performedafter the formation of the first conductive layer to form a metalsilicide layer between the first conductive layer and each of thesource/drain regions SD1 to SD4. For example, the metal silicide layermay include at least one of titanium silicide, tantalum silicide, ortungsten silicide.

Even though not shown in the drawings, interconnections respectivelyconnected to the first to fifth source/drain contacts CT1 to CT5 may beformed on the second interlayer insulating layer 150. Theinterconnections may include a conductive material.

FIG. 11 is an equivalent circuit diagram of a complementarymetal-oxide-semiconductor static random access memory cell (CMOS SRAMcell) including a field effect transistor according to exampleembodiments. Referring to FIG. 11, a CMOS SRAM cell may include a pairof driver transistors TD1 and TD2, a pair of transfer transistors TT1and TT2, and a pair of load transistors TL1 and TL2. The drivertransistors TD1 and TD2 may correspond to pull-down transistors, thetransfer transistors TT1 and TT2 may correspond to pass transistors, andthe load transistors TL1 and TL2 may correspond to pull-up transistors.The driver transistors TD1 and TD2 and the transfer transistors TT1 andTT2 may be NMOS transistors, and the load transistors TL1 and TL2 may bePMOS transistors. At least one of the driver transistors TD1 and TD2 andthe transfer transistors TT1 and TT2 may be the third transistor TR3 ofFIG. 1 according to the above embodiments, and at least one of thedriver transistors TL1 and TL2 may be the fourth transistor TR4 of FIG.1 according to the above embodiments.

The first driver transistor TD1 and the first transfer transistor TT1may be in series to each other. A source region of the first drivertransistor TD1 may be electrically connected to a ground line Vss, and adrain region of the first transfer transistor TT1 may be electricallyconnected to a first bit line BL1. The second driver transistor TD2 andthe second transfer transistor TT2 may be in series to each other. Asource region of the second driver transistor TD2 may be electricallyconnected to the ground line Vss, and a drain region of the secondtransfer transistor TT2 may be electrically connected to a second bitline BL2.

A source region and a drain region of the first load transistor TL1 maybe electrically connected to a power line Vcc and a drain region of thefirst driver transistor TD1, respectively. A source region and a drainregion of the second load transistor TL2 may be electrically connectedto the power line Vcc and a drain region of the second driver transistorTD2, respectively. The drain region of the first load transistor TL1,the drain region of the first driver transistor TD1, and a source regionof the first transfer transistor TT1 may correspond to a first node N1.The drain region of the second load transistor TL2, the drain region ofthe second driver transistor TD2, and a source region of the secondtransfer transistor TT2 may correspond to a second node N2. A gateelectrode of the first driver transistor TD1 and a gate electrode of thefirst load transistor TL1 may be electrically connected to the secondnode N2. A gate electrode of the second driver transistor TD2 and a gateelectrode of the second load transistor TL2 may be electricallyconnected to the first node N1. Gate electrodes of the first and secondtransfer transistors TT1 and TT2 may be electrically connected to a wordline WL. The first driver transistor TD1, the first transfer transistorTT1, and the first load transistor TL1 may constitute a first half-cellH1. The second driver transistor TD2, the second transfer transistorTT2, and the second load transistor TL2 may constitute a secondhalf-cell H2.

FIG. 12 is a schematic block diagram illustrating an electronic systemincluding a semiconductor device according to embodiments.

Referring to FIG. 12, an electronic system 1100 according to anembodiment may include a controller 1110, an input/output (I/O) unit1120, a memory device 1130, an interface unit 1140, and a data bus 1150.At least two of the controller 1110, the I/O unit 1120, the memorydevice 1130, and the interface unit 1140 may communicate with each otherthrough the data bus 1150. The data bus 1150 may correspond to a paththrough which electrical signals are transmitted.

The controller 1110 may include at least one of a microprocessor, adigital signal processor, a microcontroller, or other logic deviceshaving a similar function to any one thereof. The I/O unit 1120 mayinclude a keypad, a keyboard and/or a display device. The memory device1130 may store data and/or commands. The interface unit 1140 maytransmit electrical data to a communication network or may receiveelectrical data from a communication network. The interface unit 1140may operate by wireless or cable. For example, the interface unit 1140may include an antenna or a wireless/cable transceiver. Although notshown in the drawings, the electronic system 1100 may further include afast dynamic random access memory (DRAM) device and/or a fast SRAMdevice which acts as a cache memory for improving an operation of thecontroller 1110. At least one of the semiconductor devices according tothe aforementioned embodiments may be provided in the memory device 1130and/or may be provided in the controller 1110 and/or the I/O 1120.

The electronic system 1100 may be applied to a personal digitalassistant (PDA), a portable computer, a web tablet, a wireless phone, amobile phone, a digital music player, a memory card, or other electronicproducts receiving or transmitting information data by wireless.

FIG. 13 is a schematic block diagram illustrating an electronic deviceincluding a semiconductor device according to embodiments.

Referring to FIG. 13, an electronic device 1200 may include asemiconductor chip 1210. The semiconductor device 1210 may include aprocessor 1211, an embedded memory 1213, a cache memory 1215, and aninput/output (I/O) terminal 1217.

The processor 1211 may include one or more processor cores C1 to Cn. Theone or more process cores C1 to Cn may process electrical data and/orelectrical signals.

The electronic device 1200 may perform a specific function by means ofthe processed data and signals. For example, the processor 1211 may bean application processor.

The embedded memory 1213 may exchange first data DAT1 with the processor1211. The first data DAT1 may be data processed or to be processed bythe one or more processor cores C1 to Cn. The embedded memory 1213 maymanage the first data DAT1. For example, the embedded memory 1213 maybuffer the first data DAT1. In other words, the embedded memory 1213 mayact as a buffer memory or a working memory of the processor 1211.

In some embodiments, the electronic device 1200 may be applied to awearable electronic device. The wearable electronic device may mainlyperform a function requiring a relatively small quantity of operations.Thus, if the electronic device 1200 is applied to the wearableelectronic device, the embedded memory 1213 may not have a great buffercapacity.

The embedded memory 1213 may be a SRAM. An operating speed of the SRAMmay be faster than that of a DRAM. When the SRAM is embedded in thesemiconductor chip 1210, it is possible to realize the electronic device1200 having a small size and a fast operating speed. In addition, whenthe SRAM is embedded in the semiconductor chip 1210, consumption of anactive power of the electronic device 1200 may be reduced. The SRAM mayinclude the semiconductor device according to the above mentionedembodiments.

The cache memory 1215 may be mounted on the semiconductor chip 1210along with the one or more process cores C1 to Cn. The cache memory 1215may store cache data DATc. The cache data DATc may be data used by theone or more process cores C1 to Cn. The cache memory 1215 may have arelatively small capacity but may have a very fast operating speed. Thecache memory 1215 may include a SRAM including the semiconductor deviceaccording to the above mentioned embodiments. When the cache memory 1215is used, it is possible to reduce an accessing number and an accessingtime of the processor 1211 with respect to the embedded memory 1213.Thus, the operating speed of the electronic device 1200 may be improvedwhen the cache memory 1215 is used.

The I/O terminal 1217 may control an operation of supplying an operatingvoltage to the processor 1211. In other words, the processor cores C1 toCn of the processor 1211 may be stably supplied with the voltage throughthe I/O terminal 1217. The I/O terminal 1217 may include the first andsecond transistors TR1 and TR2 of FIG. 1 according to the abovementioned embodiments.

In FIG. 13, the cache memory 1215 is distinguished from the processor1211 for the purpose of ease and convenience in explanation. However, inother embodiments, the cache memory 1215 may be configured to beincluded in the processor 1211. In other words, embodiments are notlimited to those illustrated in FIG. 13.

The processor 1211, the embedded memory 1213, and the cache memory 1215may transmit electrical data on the basis of at least one of variousinterface protocols. For example, the processor 1211, the embeddedmemory 1213, and the cache memory 1215 may transmit electrical data onthe basis of at least one interface protocol of universal serial bus(USB), small computer system interface (SCSI), peripheral componentinterconnect (PCI) express, advanced technology attachment (ATA),parallel ATA (PATA), serial ATA (SATA), serial attached SCSI (SAS),integrated drive electronics (IDE), or universal flash storage (UFS).

The electronic system 1100 of FIG. 12 may be applied to electroniccontrol systems of various electronic devices. FIG. 14 illustrates amobile phone 2000 implemented with then electronic system 1100 of FIG.12. In other embodiments, the electronic system 1100 of FIG. 12 may beapplied to a tablet or smart tablet 3000 illustrated in FIG. 15 and/or anotebook computer 4000 illustrated in FIG. 16.

According to example embodiments, the source/drain contacts connected incommon to the plurality of source/drain regions of each region may berealized as various shapes. Thus, a contact area between eachsource/drain contact and the source/drain regions disposed thereundercan be adjusted to realize a source/drain contact resistance desired ineach region. As a result, electrical characteristics of thesemiconductor device may be optimized to improve reliability of thesemiconductor device.

Example embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation. In someinstances, as would be apparent to one of ordinary skill in the art asof the filing of the present application, features, characteristics,and/or elements described in connection with a particular embodiment maybe used singly or in combination with features, characteristics, and/orelements described in connection with other embodiments unless otherwisespecifically indicated. Accordingly, it will be understood by those ofskill in the art that various changes in form and details may be madewithout departing from the spirit and scope of the present invention asset forth in the following claims.

1. A semiconductor device, comprising: a plurality of active patternsprotruding from a substrate; a gate structure intersecting the pluralityof active patterns; a plurality of source/drain regions respectively onthe plurality of active patterns at opposite sides of the gatestructure; and source/drain contacts intersecting the plurality ofactive patterns, each of the source/drain contacts connected in commonto the source/drain regions thereunder, wherein each of the plurality ofsource/drain regions includes: a first portion in contact with a topsurface of the active pattern thereunder, the first portion having awidth substantially increasing as a distance from the substrateincreases, and a second portion extending from the first portion, thesecond portion having a width substantially decreasing as a distancefrom the substrate increases, and wherein bottom surfaces of thesource/drain contacts are lower than an interface between the first andsecond portions.
 2. The semiconductor device as claimed in claim 1,wherein the bottom surfaces of the source/drain contacts are higher thanthe top surfaces of the plurality of the active patterns.
 3. Thesemiconductor device as claimed in claim 1, wherein the bottom surfacesof the source/drain contacts are flat surfaces substantially parallel toa top surface of the substrate.
 4. The semiconductor device as claimedin claim 1, wherein the bottom surfaces of the source/drain contactsinclude uneven and curved surfaces.
 5. (canceled)
 6. The semiconductordevice as claimed in claim 1, wherein each of the source/drain regionsfurther comprises a third portion at a lower level than the top surfacesof the plurality of active patterns, the third portion being in contactwith sidewalls of the active pattern under each of the source/drainregions, wherein a lowermost end of the third portion is spaced apartfrom the sidewalls of the active pattern. 7.-8. (canceled)
 9. Thesemiconductor device as claimed in claim 1, further comprising a deviceisolation pattern on the substrate to partially cover sidewalls of theplurality of active patterns, the device isolation pattern including: afirst region under the gate structure, and second regions at oppositesides of the gate structure, at least one of the second regionsincluding a plurality of recess regions having bottom surfaces lowerthan a top surface of the first region.
 10. The semiconductor device asclaimed in claim 9, wherein the plurality of recess regions includes:first recess regions among the plurality of active patterns; and secondrecess regions at opposite sides of the plurality of active patterns,bottom surfaces of the first recess regions being higher than bottomsurfaces of the second recess regions.
 11. (canceled)
 12. Thesemiconductor device as claimed in claim 10, wherein the first recessregions include an air gap.
 13. The semiconductor device as claimed inclaim 12, wherein at least one of the source/drain contacts includes anextension extending into the air gap.
 14. The semiconductor device asclaimed in claim 12, further comprising a contact etch stop layercovering inner surfaces of the first and second recess regions andextending onto the plurality of source/drain regions and sidewalls ofthe gate structure, the air gap being defined by the contact etch stoplayer.
 15. The semiconductor device as claimed in claim 1, wherein thegate structure includes: a gate electrode intersecting the plurality ofactive patterns; and a gate dielectric pattern between the gateelectrode and the plurality of active patterns, the gate dielectricpattern including: a first sub-gate dielectric pattern, and a secondsub-gate dielectric pattern having a higher a dielectric constant thanthat of the first sub-gate dielectric pattern.
 16. A semiconductordevice, comprising: a substrate including a first region and a secondregion different from each other; a plurality of first active patternsprotruding from the substrate of the first region, the first activepatterns being spaced apart from each other at equal distances; aplurality of second active patterns protruding from the substrate of thesecond region, the second active patterns being spaced apart from eachother at different distances; a first gate structure intersecting theplurality of first active patterns; a second gate structure intersectingthe plurality of second active patterns; a plurality of firstsource/drain regions respectively on the plurality of first activepatterns at one side of the first gate structure; a plurality of secondsource/drain regions respectively on the plurality of second activepatterns at one side of the second gate structure; a first source/draincontact intersecting the plurality of first active patterns, the firstsource/drain contact being connected in common to the plurality of firstsource/drain regions; and a second source/drain contact intersecting theplurality of second active patterns, the second source/drain contactbeing connected in common to the plurality of second source/drainregions, wherein a top surface of the first source/drain contact islower than a top surface of the second source/drain contact. 17.-23.(canceled)
 24. The semiconductor device as claimed in claim 16, whereineach of the plurality of first source/drain regions includes: a firstportion in contact with a top surface of the first active patternthereunder, the first portion having a width substantially increasing asa distance from the substrate increases; and a second portion extendingfrom the first portion, the second portion having a width substantiallydecreasing as a distance from the substrate increases, wherein a bottomsurface of the first source/drain contact is lower than an interfacebetween the first and second portions. 25.-28. (canceled)
 29. Thesemiconductor device as claimed in claim 16, wherein the plurality ofsecond active patterns include: a pair of first sub-active patternsspaced apart from each other by a first distance; and a secondsub-active pattern spaced apart from one of the pair of first sub-activepatterns by a second distance greater than the first distance, whereinthe plurality of second source/drain regions include first, second, andthird sub-source/drain regions on the pair of first sub-active patternsand the second sub-active pattern, respectively, and wherein aconductivity type of the first and second sub-source/drain regions isdifferent from that of the third sub-source/drain region.
 30. Thesemiconductor device as claimed in claim 29, wherein the secondsource/drain contact includes an extension extending between the secondsub-active pattern and the first sub-active pattern adjacent to thesecond sub-active pattern.
 31. A semiconductor device, comprising: aplurality of active patterns protruding from a substrate; a gatestructure intersecting the plurality of active patterns; a plurality ofsource/drain regions respectively on the plurality of active patterns atopposite sides of the gate structure; and source/drain contactsintersecting the plurality of active patterns, each of the source/draincontacts being connected in common to the source/drain regionsthereunder, wherein each of the plurality of source/drain regionsincludes at least one sidewalls with a triangular profile, thetriangular profile having a sharp edge extending away from a sidewall ofa corresponding source/drain contact, and wherein distances between abottom of the substrate and corresponding lowermost surfaces of thesource/drain contacts are smaller than respective distances of thebottom of the substrate and corresponding sharp edges.
 32. Thesemiconductor device as claimed in claim 31, wherein each of theplurality of source/drain regions includes: a first portion in contactwith a top surface of the active pattern thereunder, the first portionhaving a width substantially increasing as a distance from the bottom ofthe substrate increases; and a second portion extending from the firstportion, the second portion having a width substantially decreasing as adistance from the bottom of the substrate increases, wherein the sharpedges of the triangular profiles are at an interface between the firstand second portions.
 33. The semiconductor device as claimed in claim31, further comprising air gaps among the plurality of source/drainregions, each source/drain contact being on at least one correspondingair gap.
 34. The semiconductor device as claimed in claim 31, wherein atleast one of bottom surfaces of the source/drain contacts has adifferent profile than other source/drain contacts.
 35. Thesemiconductor device as claimed in claim 34, wherein the at least one ofthe bottom surfaces of the source/drain contacts having a differentprofile has a larger contact area with a corresponding source/drainregion thereunder.